Enhanced Synchronous Serial Interface (ESSI)
Additional synchronization signals delineate the word frames. The Normal mode of operation
transfers data at a periodic rate, one word per period. The Network mode is similar in that it is
also for periodic transfers; however, it supports up to 32 words (time slots) per period. The
Network mode can be used to build time division multiplexed (TDM) networks. In contrast, the
On-Demand mode is for nonperiodic transfers of data. This mode, which offers a subset of the
Freescale Serial Peripheral Interface (SPI) protocol, can transfer data serially at high speed when
the data become available. Since each ESSI unit can be configured with one receiver and three
transmitters, the two units can be used together for surround sound applications (which need two
digital input channels and six digital output channels).
7.1 ESSI Enhancements
The DSP56000 SSI is enhanced in the following ways to make the ESSI:
Network enhancements
— Time slot mask registers (receive and transmit)
— End-of-frame interrupt
— Drive enable signal (used with transmitter 0)
Audio enhancements
— Three transmitters per ESSI (for six-channel surround-sound)
General enhancements
— Can trigger DMA interrupts (receive or transmit)
— Separate exception enable bits
Other changes
— One divide-by-2 step is removed from the internal clock source chain
— The CRA[PSR] bit definition is reversed
— Gated-Clock mode is not available
7.2 ESSI Data and Control Signals
Three to six signals are required for ESSI operation, depending on the operating mode selected.
The serial transmit data ( STD ) signal and serial control ( SC0 and SC1 ) signals are fully
synchronized to the clock if they are programmed as transmit-data signals.
7.2.1 Serial Transmit Data Signal (STD)
The STD signal transmits data from the serial transmit shift register. STD is an output when data is
transmitted from the TX0 shift register. With an internally-generated bit clock, the STD signal
becomes a high impedance output signal for a full clock period after the last data bit is
transmitted if another data word does not follow immediately. If sequential data words are
DSP56311 User’s Manual, Rev. 2
7-2
Freescale Semiconductor
相关PDF资料
DSPAUDIOEVMMB1E BOARD MOTHER DSP563XX
DSPIC30F2010 DEVELOPMENT KIT KIT DEV EMBEDDED C
DSTRM-KT-0181A DSTREAM DEBUG AND TRACE UNIT
DSUT1CSU SURGE SUPPR NETWORK W/GROUND
DTEL2 SURGE SUPPRESSOR PHONE RJ11/RJ45
DV003001 PROGRAMMER PICSTART PLUS 16C/17C
DV164035 MPLAB ICD3 IN-CIRC DEBUGGER
DV164039 KIT DEV PIC24FJ256DA210
相关代理商/技术参数
DSP56311EVMIG_D 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311EVMIG DSP56311EVM Sample Code
DSP56311EVMUM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Evaluation Module Hardware Reference Manual
DSP56311FACT 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Higher performance programmable DSP for demanding voice and data applications
DSP56311UM 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 24-Bit Digital Signal Processor Users Manual
DSP56311UMAD 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56311 Users Manual Addendum
DSP56311VF150 功能描述:数字信号处理器和控制器 - DSP, DSC 150Mhz/300MMACS 150Mhz EFCOP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150B1 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSP56311VF150R2 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT